1. Technical Field
The present disclosure relates to a semiconductor device and a method of manufacturing the same, and, in particular, a semiconductor device including a three-dimensional memory device and a method of manufacturing the same.
2. Related Art
A non-volatile memory device may maintain already-stored data in a power-off state thereof. As a 2D memory device with a single layer memory cell on a silicon substrate reaches a maximum degree of integration, there has recently been proposed a 3-dimensional non-volatile memory device having vertical memory cells stacked from and on a silicon substrate.
The 3D non-volatile memory device includes a stack of vertical alternations of conductive layers and insulating layers, and a vertical channel layer passes through the conductive layers and insulating layers. Further, a charge trapping layer may surround the vertical channel layer so as to store data. However, the charge trapping layers of stacked memory cells may have interconnections, and, hence, charges may travel between the memory cells. This may lead to stored data damages. Further, the vertical channel layer may be thinner and hence may not achieve sufficient cell current. Further, a breakdown voltage may possibly not be established between adjacent gate electrodes. Thus, those gate electrodes having a voltage breakdown may result in a performance degradation of the memory device.